The present invention relates to methods for fabricating semiconductor devices, and semiconductor substrates. Particularly, the present invention relates to methods for fabricating semiconductor devices that prevent the decrease in reliability of components due to contamination of metal impurities during processing, and semiconductor substrates used in the semiconductor devices.
In recent years, together with the miniaturization of semiconductor components and the enlargement of semiconductor substrate (wafer), and due to the tendency of decreasing the diffusion length of impurities determining the conductivity type of semiconductor, or the prevention of the generation of thermal stress to wafers and the adverse effects to the electrical characteristics of the component caused by the application of thermal treatment, there is a tendency to decrease the temperature and the time of thermal treatment in a semiconductor fabricating process.
Generally, by sufficiently applying thermal treatment to the wafer, defects known as bulk microdefect (BMD) are generated due to the precipitation of oxygen in the lattices within the semiconductor substrate, and the BMD function as gettering sites. As a result, even if metal impurities generated during the fabricating process are deposited on the wafer, the deposited metal impurities are captured by the gettering sites, and thus the decrease in reliability of the gate insulating film and the like can be prevented. Such gettering capability of the BMD can be realized as long as the concentration of the BMD is approximately 1×108 cm−3. However, in order to achieve such concentration of growth, generally, a thermal treatment of relatively high temperature for a relatively long period of time, such as a temperature of 1000° C. or more for a few hours, is required.
The conventional thermal treatment used in the method for fabricating semiconductor device that includes a step of forming a gate insulating film is described hereinafter.
FIG. 7 shows a typical thermal treatment performed on a device having, for example, a design rule of 0.15 μm. In the case where the wafer is made of silicon (Si), the thermal treatment shown in FIG. 7 is usually performed at a temperature of 900° C. for less than 100 minutes, and in the case where the temperature exceeded 1000° C., a rapid thermal processing (RTP) of 1 second to 30 seconds is performed. In such conventional thermal treatment, since the BMD cannot be sufficiently grown, the concentration of the BMD, which function as gettering sites, become 1×106 cm−3 or less.
Moreover, in the case where a RTP is performed during the initial thermal treatment in the fabricating process, due to high increasing rate of temperature in the thermal treatment, the precipitation nuclei of the BMD within the wafer are dissolved and BMD growth cannot be achieved. Hence a sufficient gettering capability cannot be achieved in a miniature device process of which thermal budget is small, such that short period of thermal treatments such as RTP are intensively used and the temperature of the thermal treatment is relatively low. In other words, such process is extremely prone to metal contamination and the like. Here, the thermal budget refers to the amount of thermal treatment represented by the product of the temperature and the time for thermal treatment.
For example, problems such as the increase in current leakage due to metal contamination of the thinned gate insulating film composing the MOS (metal oxide semiconductor) transistor, and the decrease in reliability of the gate insulating film will occur.
In order to solve this problem, the thermal budget is increased by increasing the temperature and time period of the thermal treatment during the process. However, this in turn increases the diffusion length of the impurity ions that determine the conductivity type and fails to essentially solve the problem, thus becoming a serious problem in miniaturized CMOS (complementary metal oxide semiconductor) device.
Further, even if the precipitation nuclei of the gettering sites are formed in the silicon wafer, as shown in FIGS. 8A to 8C, other problems exist in the conventional high temperature annealing. For example, as shown in FIG. 8A, a wafer 100 composed of silicon having precipitation nuclei 101A of gettering sites composed of nitrogen, carbon, or oxygen is being prepared.
Next, as shown in FIG. 8B, annealing is performed approximately under a temperature of 1200° C. for 60 minutes to form gettering sites 101B composed of BMD, in which the precipitation nuclei 101A are grown, in a region several tens of μm from the surface of the wafer 100, and to form a Denuded Zone (DZ) 100a including no defects in the upper portion of the wafer 100.
However, as shown in FIG. 8C, the distance from the wafer surface to the gettering sites 101B is long, and metal impurities 110 having relatively small diffusion coefficient, such as iron (Fe), cannot be sufficiently diffused to the gettering sites 101B in a typical fabricating process, specifically in the thermal treatment within the miniaturized CMOS process.